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View Partner Search: PS-EG-1751
PS overview
PS details
PROPOSAL AT A GLANCE
Proposal name:
Subject:
Develop design methodologies for Network-on-Chip.
Developing high-performance, low-power Network-on-Chip is the primary target of the project. Different issues , such as interconnects and noise are going to be considered.
The project aims to developing new design methodologies to build networks on-chip and will address the data management, storage and processing functions of smart systems.
Developing figures of merit to measure the efficiency of building network on chip is an important target. Tools should be developed to reduce the design phase of systems-on-chip.
The tools will be used by the designers to reduce the time to market. The tools will help in pre-industrial validation of new design concepts suitable for large-scale production of micro-/nano-scale systems.
The developed tools will enable data management, storage and processing functions of smart micro/nanosystems enabling wireless access and facilitating intelligent networking.
PROJECT DESCRIPTION
Proposal Outline:
This project aim to develop figures of merit to build Networks-on-Chip. Tools should be developed to define when networks on chips are necessary. Different design methodologies should be enhanced to design effiecint networks on chip. This will be based on the traffic on chip and the size of it. The developed tools will enable data management, storage and processing functions of smart micro/nanosystems enabling wireless access and facilitating intelligent networking.
Keywords:
VLSI
System-on-Chip (SoC)
Digital electronics
Network-on-Chip (NoC)
ASIC design
CMOS Microelectronic Circuits
Interconnects
On-Chip communication
PARTNER PROFILE SOUGHT
Required skills and Expertise:
Three parteners are required.
The first should be an expert in digital electronics, logic design, DFT, integrated circuits design, interconnect and physical design, ASIC design, VLSI, Electromagnetic effects, RTL, and Validation.
The second should be expert in basics of computer networks, routing, addresing, scheduling, congestion control, and ISO-OSI reference model.
The third partener should be expert in CAD tools and programming.
Description of work to be carried out by the partner(s) sought:
The first partner would be involved in carrying out research and development work to produce accurate model for traffic on-chip.
The second partner would be involved in carrying out research and development work to determine and define quality of service on-chip.
A third partner would be involved in implementing VLSI/SoC design. A manufacturing facility for fabrication and testing could be required.
Type of partner(s) sought:
Research institute, university and industry. Research institute are university are must. Industry is an option.
