Semiconductor manufacturers were traditionally looking at increasing the equipment T/P to streamline their production flow and reduce the cycle time. However, there is a limit as to how much T/P can be improved and the Semiconductor manufacturers are looking for new ways to improve their revenue and ROI.
The photolithography cell is one of those areas where Semiconductor manufacturers look for new ways to optimize. It constitute one of the largest expenses in the FAB and is the most critical step in the Semiconductor manufacturing steps. Metrology inspection tools are used for qualifying wafers and masks at the Photo cell before and after the photolithography process to assure high product yield at the end of the line.
Semiconductor FABs have, traditionally, used stand alone Metrology inspection tools resulting in long delays between the photolithography process and the availability of corrections and wafer disposition. In many cases the feed-back data is only available a long time after a batch of wafer was printed and no real-time corrections is available resulting in a reworked batch.

To remedy the above culprits Semiconductor manufacturers are looking into a more integrated approach where the Metrology Inspection tools are integrated with the Photolithography tool and wafers are inspected as soon as they are made on a wafer-by-wafer basis. The over all cycle time is thus shortened, there are less material movements between stand-alone tools, the entire litho-cell cycle time variability is reduced and feedback and disposition information is available sooner for the Semiconductor manufacturer to take corrective actions more rapidly. The level of material-at-risk as well as WIP would be significantly reduced and Batch processing related disadvantages overcome.
The Semiconductor industry has not yet embraced the Integrated Metrology concept due to some concerns and risks that may offset the benefits. The first concern is that manufacturers are not clear about the ROI of IM as there are no good models available to show it. IM installation, qualification and maintenance are of prime concern and models do not yet exist for these.
We therefore propose to develop a Return of Investment (ROI) and Cost of Ownership (COO) model for the Semiconductor industry handling the above critical aspects.

Project Deliverables will include:
• ROI and COO model to the Semiconductor Manufacturer from using IM
• ROI Model to the Semiconductor equipment manufacturer from IM products
• Software simulation tool for processing FAB data
• Reliability model and requirements for an IM (characterization)
• Installation, qualification and maintenance models and concepts for IM
• FAB Material flow management and rerouting analysis and modeling for the IM use case
• Use cases, models and processes for Integrated Metrology approach challenges including, but not limited to, recipe management, matching, service, preventive maintenance, etc.
• Analysis and model for optimum wafer sample plan under given time constraints to achieve statistical confidence in collected data.
• Analysis and modeling of Manufacturing process variability improvement with IM
• IM T/P Model. The IM should not slow down the litho-cell.

Partner 1:

Academic/Research institute, Operation Research specialists.

Partner 2:

Software company specializes in software simulation tools for the Semiconductor industry

Partner 3:

Academic/Research institute specializes in building models for the Semiconductor industry

Partner 1:

Model optimized wafer flow and rerouting for the IM use case. Research and model manufacturing process variability and resulting improvement by Integrated Metrology.

Partner 2:

Develop a software simulation tool for validating the model developed

Partner 3:

Research and model reliability impact and remedy processes to the Integrated Metrology use case.

Academic/Research institutes, Software companies